CMOS integrated circuits are a logic family that is widely used in designing electronic circuits because it uses very little power. Emitter Coupled Logic (ECL) circuits use much more power, however, ECL is much faster than CMOS and is used when CMOS is not fast enough for the circuit. The reduced voltage swing of ECL causes less radiation of signals connected through a printed circuit board. Also, ECL is designed to drive transmission lines having low impedance, so it provides better signal characteristics between integrated circuits at high frequencies. For example, ECL is used when providing high frequency signals to generate video signals for very high resolution cathode ray tubes used in computer workstations.
CMOS integrated circuits typically use a 5 volt supply for operation, and the logic levels change over the entire range of this voltage, that is, 0 volts is output for a logic zero, and 5 volts is output for a logic one. ECL has traditionally used a -5.2 volt supply. The ECL circuits reference their logic levels from ground and output is over a much narrower range, having worst case values of -1.1 for a logic one, and -1.5 for a logic zero.
ECL circuits can be combined with CMOS circuits by also using the CMOS +5 volt supply voltage for the ECL, and having the ECL reference its signals to the +5 volt supply, rather than ground. When this is done, the ECL logic one will be 3.9 volts, and the ECL logic zero will be 3.5 volts. This method provides the speed benefits of ECL while allowing the circuits to be combined into a single integrated circuit. ECL used in this manner is sometimes called "pseudo" ECL, positive ECL or shifted ECL.
Because of the narrow range between worst case values for a logic one and a logic zero, variations in the CMOS fabrication process can seriously affect whether the ECL circuit will function correctly. If the process variation causes the CMOS transistors to be "fast" or "slow" although still within the CMOS fabrication process tolerance, the circuits that convert between CMOS levels and ECL levels may not provide sufficient margin to function properly.
There is a need in the art then for a conversion circuit that converts between shifted ECL and CMOS voltage levels, fabricated within a CMOS integrated circuit, that provides adequate output margins over all ranges of fabrication process variations. The present invention meets this and other needs.